1. Technical Field
The present invention relates to a circuit for driving pull-up and pull-down transistors of an I/O buffer in an integrated circuit (IC). More particularly, the present invention relates to an I/O driver circuit with components to prevent crowbar current occurring when both the pull-up and pull-down transistor are momentarily turned on together during a transition of the I/O buffer.
2. Related Art
FIG. 1 shows a block diagram of typical components of an I/O driver. The I/O driver circuitry is shown providing an output from logic 2 of an IC. The I/O driver is illustrated with logic circuitry 2, such as that provided in a Complex Programmable Logic Device (CPLD) or an Field Programmable Gate Array (FPGA), although a similar I/O driver can be used with other circuit types, such as a microprocessor or an ASIC.
The I/O driver circuit shown in FIG. 1 initially includes level shifters 4 and 14 for transitioning a voltage level from Vdd, provided to logic 2, to Vcco, provided to the output pad 20, to make the IC compatible with other chips that operate at different voltage levels. The level shifter 4 is provided to shut off completely any PMOS transistor in the pull-up pre-driver, while the level shifter 14 is provided to match the timing of the pull-up pre-driver 6 relative to the pull-down pre-driver 16 when Vcco is significantly higher than Vdd. The level shifters 4 and 14 are provided to make the IC compatible with other chips that operate at different voltage levels. For example, the internal logic 2 may operate at 2.5 volts, while the pad 20 is connected to a chip with input voltage requirements of 3.0 volts or 5.0 volts. If the IC containing the logic 2 is only designed to operate with components operating at the same voltage level, the level shifters 4 and 14 are not needed.
The I/O driver circuitry further includes pull-up and pull-down pre-driver circuits 6 and 16 that function to apply appropriate voltage level and provide appropriate current capacity to transistors in the pull-up driver 8 and pull-down driver 18 so that the signal on the pad 20 has HI and LO transitions corresponding with the data signal provided from the logic 2. The pull-up and pull-down pre-driver circuits 6 and 16 also function to transition transistors in the pull-up and pull-down drivers 8 and 18 so that crowbar current does not occur.
The pull-up and pull-down driver circuits 8 and 18 can be as simple as shown in FIG. 2. The PMOS pull-up transistor 22 forms the pull-up driver 8, while the NMOS pull-down transistor 32 forms the pull-down driver 18 of FIG. 1. The pull-up and pull-down driver transistors 22 and 32 are typically large in size in order to drive the pad and to sink or source current required for an IC device. However, if the signals Pu_b and Pd change at the same time, there is a moment that both the PMOS transistor 22 and NMOS transistor 32 are ON that momentarily causes an unwanted crowbar current, labeled Icrowbar, to flow directly from Vcco to Gnd. Not only does Icrowbar waste power, it also causes Vcco and ground bounce.
To eliminate crowbar, Pu_b and Pd are generated by pre-driver circuits 6 and 16 of FIG. 1 without a transition overlap, as shown in FIG. 3. In FIG. 3 with the signal from logic 2 being LO for some time, Pu_b is HI turning off PMOS transistor 22, while Pd is HI turning on NMOS driver transistor 32 to drive the pad LO. With a transition of the signal from logic 2 to a HI, Pd initially goes LO to turn off NMOS transistor 32 first before Pu_b goes LO to turn on PMOS transistor 22 so that transistors 22 and 32 are not on together. Pu_b transitioning to LO turns on PMOS transistor 22 and drives the pad HI. When the signal from logic 2 transitions back to LO, Pu_b initially goes HI to turn off PMOS transistor 22 before Pd goes HI to turn on NMOS transistor 32 so that transistors 22 and 32 again are not on together. Pd transitioning to HI turns on NMOS transistor 32 and drives the pad LO.
Another configuration for a pull-up and pull-down drivers 8 and 18 is shown in FIG. 4. In FIG. 4, the pull-up and pull-down drivers are split into AC and DC driver portions. The AC driver transistors 24 and 34 would turn on quickly first before a later turn on of the DC driver transistors 22 and 32. The AC driver is used to meet rapid rise and fall time specifications, and typically use smaller transistors. The DC driver transistors are much larger to sustain driving a large load on the pad once a transition occurs. The larger DC driver transistors would transition slower, based on their size, and are turned on only to sustain a large load after transitioning. With rapid transitioning of the AC drivers, the DC driver transistors could potentially remain off. If only one set of driver transistors are desired and rapid transition specifications are not needed, the large DC transistors 22 and 32 are used alone as shown in FIG. 2. FIG. 4 adds the AC PMOS pull-up transistor 24 and NMOS pull-down transistor 34. For convenience, components carried over from FIG. 2 to FIG. 4 are similarly labeled, as will be components carried over in subsequent drawings. In some versions of a split AC and DC driver, the AC pull-up transistor 24 is an NMOS device which provides a more rapid transition than a PMOS device, while the DC pull-up transistor 22 remains a PMOS device which does not experience a transistor threshold drop of an NMOS transistor.
The preferred timing for the components of FIG. 4 is illustrated in FIG. 5. In FIG. 5 with the signal from logic 2 being LO for some time, Pu_1b and Pu2b are HI turning off PMOS transistors 22 and 24, while Pd1 and Pd2 are HI turning on NMOS transistors 32 and 34 to maintain the pad LO. With a transition of logic 2 to a HI, Pd1 and Pd2 initially go LO together to turn off NMOS transistors 32 and 34 before either of Pu_1b or Pu2—b go LO to turn on PMOS transistors 22 and 24. Similar to the Pu_b and Pd signals of FIG. 3, the signals Pd1, Pd2, Pu_1b and Pu_2b of FIG. 5 are provided to ensure that none of the PMOS and NMOS transistors turn on together to prevent crowbar current. So, the AC driver PMOS transistor 24 is turned on by Pu_1b going LO after Pd1 and Pd2 are LO (turning off both the NMOS transistors 32 and 34). Pu_1b driving the AC PMOS transistor 24 first ensures a fast rise time on the pad relative to FIG. 3. Pu_2b transitions later than Pu_1b to sustain the pad HI with the large DC PMOS driver transistor 24. When the signal from logic 2 transitions back to LO, Pu_1b and Pu_2b initially go HI together. To prevent crowbar, Pd1 and Pd2 do not begin to go HI to turn on the NMOS transistors 32 and 34 until after the PMOS transistors 22 and 24 are fully off due to Pu_1b and Pu_2b. Pd1 initially goes HI to turn on the AC driver NMOS transistor 34 first, while Pd2 transitions to HI later to sustain the pad LO using DC driver NMOS transistor 32.
The level shifter circuits 4 and 14 and pre-driver circuits 6 and 16 of FIG. 1, which provide the voltages shown in FIG. 5, are very challenging to implement. Many IC designers have achieved providing the voltages using circuitry that trades off the crowbar current in the I/O drivers 8 and 18 with some crowbar current generated in the level shifter 4 and 14 and in the pre-drivers 6 and 16 instead.
FIG. 6 shows a typical configuration of circuitry for level shifters 4 and 14 of FIG. 1, while FIG. 7 shows a configuration for the level shifters 4 and 14 modified to prevent crowbar current in the I/O drivers 8 and 18 at the expense of some crowbar current created in the level shifters 4 and 14. In FIG. 6, the input signal IN (provided from logic circuit 2 at voltage Vdd) is directed to the gates of NMOS transistors 40 and 44 of a cross coupled differential amplifier that are at voltage level Vcco needed at the pad. The input signal is further provided through an inverter 43 supplied at Vdd to the gates of PMOS transistors 46 and 50. The drains of PMOS transistors 42 and 48 provide complementary outputs out_R and out_L from the level shifter.
In operation with the circuit of FIG. 6, when IN transitions from HI to LO (Vdd to 0), the gate of transistor 46 at the output of inverter 43 shifts from LO to Hi to turn transistor 46 partially off, therefore weakening the pull up on node out_R via transistor 48, which remains ON (since out_L was 0V). Thus, the NMOS transistor 50 has to be big enough to win over the weakened pull-up by transistors 46 and 48 to pull out_R to at least one threshold voltage (Vtp) of transistor 42 below Vcco in order to turn on transistor 42. Once transistor 42 turns ON, a positive feedback kicks in to pull out_L to Vcco and out_R to 0V via transistor 40, which is on due to IN being LO. As designed, the circuit of FIG. 6 allows for transitioning of out_R and out_L in response to a transition of IN with little or no crowbar current.
FIG. 7 modifies FIG. 6 by adding inverters 51-54 connected from out_R to the gate of transistor 42. The added inverters 51-54 provide a switching delay to prevent crowbar in subsequent pre-driver or pull-up driver circuits that might otherwise experience crowbar when modified to provide faster switching. The design of FIG. 7 further enables the level shifter to assist the pull-up and pull-down drivers 8 and 18 in driving large loads.
For operation of the circuitry of FIG. 7, IN is initially assumed to be LO. With IN LO, the output of inverter 54 is LO and out_L remains HI. When IN transitions to HI, the following events occur. First, NMOS transistor 44 turns on immediately. Since IN is only Vdd, the PMOS transistor 40 never shuts off completely. Transistor 42 remains on until out_R goes to HI (Vcco) after the four inverter delay through inverters 51-54. Thus, there is a crowbar current every time IN transitions from LO to HI for approximately the 4-inverter delay. The crowbar current occurring every time IN transitions from LO to HI due to the 4-inverter delay will create a significant current drain on the power supply since there may be hundreds of I/Os or more per chip.
In addition to the crowbar current created, larger transistors are required for operation of the circuitry of FIG. 7 For the level shifter with four inverter delays in FIG. 7, transistor 50 needs to pull out_R to a voltage that is below the trip point of inverter 51. Since the trip point of inverter 51 is normally a voltage lower than a Vtp drop of transistor 42 from Vcco, transistor 50 must be bigger in order for the level shifter to function properly. FIG. 8 illustrates the voltage difference needed for transistor 50 (which must now be made significantly larger) to pull down from Vcco a Vtp of transistor 42, along with the trip point of inverter 51.
FIGS. 9 and 10 show circuitry for a conventional pre-drivers 6 and 16. FIG. 9 shows the pull-up portion of the pre-driver 6 of FIG. 1, while FIG. 10 shows the pull-down portion of the pre-driver 16 with both pre-driver circuits configured to drive both an AC I/O driver and a DC I/O driver. Input signals to the pre-driver circuits are shown as separate inputs (IN_predrv.pu1, IN_predrv.pu2, IN_predrv.pd1, IN_predrv.pd2) that may be controlled by separate level shifting circuits, although a single input (IN) can be used to drive all of the pre-driver circuits together.
In the pull-up pre-driver structure of FIG. 9, the top circuitry 55 for driving the AC pull-up with the signal Pu_1 is the same as the bottom circuit 56 for driving the DC pull-up with the signal Pu_2delay, except the capacitor 59 providing a delay in the bottom circuitry, so components and operation will be described with respect to the circuit 55.
In operation with the input signal IN_predrv.pu1 LO for some time, NMOS transistors 49 and 57 will be off, node AA will be LO, PMOS transistor 58 will be on, node BB will be HI and NMOS transistor 60 will be on. With the input signal IN_predrv.pu1 to pre-driver 55 transitioning to HI, there will be a path created for crowbar current resulting from the delays created using inverters 61-63 at points AA and BB. The crowbar path is based on M going HI slightly before BB goes LO. The crowbar path is through PMOS transistors 58 and 64 and NMOS transistors 49 and 60 to ground as well as through PMOS transistors 58 and 64 and NMOS transistors 57 and 66 to ground.
Slew rate is controlled by the signals sl1-sl3 applied at the gates of transistors 71-73. The more of the transistors 71-73 that are turned on, the faster the slew rate. Note that with more of the transistors 71-73 turned on in combination with NMOS transistor 57, the more crowbar current created. The slew rate control is somewhat compromised since the control is implemented one stage removed from the actual I/O output stage.
In the pull-down pre-driver structure of FIG. 10, the left circuit 81 for driving the AC pull-down with the signal Pd_1 is the same as the right circuit 82 for driving the DC pull-down with the signal Pd_2delay, except the capacitor 83 providing a delay in the DC circuit 82, so components and operation will be described with respect to the to circuit 81.
In operation, the transistors 84 and 85 will always be on. With the input signal IN_predrv.pd1 HI for some time, PMOS transistors 86 and 88 will be off, node AA will be HI, NMOS transistors 87 and 89 will be on, BB will be LO and PMOS transistor 90 will be on. With the input signal IN_predrv.pd1 to pre-driver 81 transitioning to LO, there will be a path created for crowbar current resulting from the delays created using inverters 91-93 at points M and BB. The crowbar path is based on AA going LO slightly before BB goes HI. The crowbar path is through PMOS transistors 84 and 86 and NMOS transistors 89 and 93 to ground as well as through PMOS transistors 88 and 90 and NMOS transistors 89 and 93 to ground.
Slew rate is controlled by the signals sl1-sl3 applied at the gates of transistors 101-103. As with the pull-up pre-drivers of FIG. 9, the more slew rate control transistors turned on, the faster the slew rate. Further, as with FIG. 9, the slew rate control in FIG. 10 is somewhat compromised since the control is implemented in the pre-driver stage.
With hundreds of both the pull-up and pull-down pre-driver circuits creating crowbar current in an IC, significant power will be drained. It would be desirable to have a pre-driver circuit as well as a level shifter that prevents crowbar in pull-up and pull-down drivers, while not experiencing a trade-off of crowbar in the pre-driver or level shifter circuitry and without requiring large transistors.